The present application relates to semiconductor device fabrication, and more particularly, to fabrication of fin field effect transistors (FinFETs) having abrupt junctions self-aligned to a gate electrode.
FinFETs are a desired device architecture due to their fast switching times and high current densities. In its basic form, a FinFET includes a source region, a drain region and a fin-shaped channel region located between the source and the drain regions. A gate electrode formed over the fin regulates electron or holes flow between the source and the drain regions. A gate spacer is typically formed on sidewalls of the gate electrode to control gate-to-source/drain spacing.
As dimensions of FinFETs are scaled further down, designers facing a tradeoff between short channel effects and source/drain resistance. Greater source/drain doping to reduce resistance increases junction depth and related short channel effects. Therefore, novel device structures are needed to provide abrupt junctions while minimizing short channel effects.
The extent of the lateral diffusion of dopants from the source/drain regions toward the channel region of the FinFET is also of great concern. Since precise control of dopant profile is hard to achieve when a diffusion process is used, the channel region of the FinFET may also be doped. The channel doping in FinFETs results in carrier mobility decrease and therefore performance penalty. The channel doping also leads to random dopant fluctuation (RDF) which is one of major contributors effecting chip variability. It is thus desirable to fabricate FinFETs with little or no channel doping to avoid the penalties caused by the channel doping.